The present invention relates to a method for forming a multilevel interconnection of a semiconductor device.
Generally, the circuit structure of the semiconductor device recently intends to have a multilevel (multilayered) interconnection structure in accordance with the need for high density and integration. In the multilayered interconnection structure, a filling technique relating to a contact hole and a via hole is regarded as important to improve an electrical connection between the interconnection and the device or between interconnections. In this case, the contact hole means a connecting portion for connecting a device of a lower layer to an aluminum interconnection of an upper layer. Also, the via hole means a connecting portion for connecting an aluminum interconnection of a lower layer to an aluminum interconnection of an upper layer. For this reason, for example, an aluminum film is formed by sputtering so as to fill the hole with the aluminum film, or a tungsten film is formed by CVD (Chemical Vapor Deposition) so as to fill the hole with the tungsten film.
As a method for filling a connection hole between interconnections, the following three methods have been known.
(Sputtering Method)
An aluminum film is heated at high temperature of 400 to 450.degree. C. or more so as to be formed on a substrate by sputtering, and a hole is filled with the aluminum film. Or, an interior of a processing container is set to be more than one atmospheric pressure. Under this state, the aluminum film is formed on the substrate by sputtering, and the hole is filled with the aluminum film.
(Selective Tungsten Film Forming Method)
By use of such a property that the tungsten film is selectively deposited on a surface of conductive material, the tungsten film is deposited on the surface of the conductive material of a bottom portion of the hole so as to fill the hole.
(Entire Surface Film Formation Etch Back-Method)
WF.sub.6 gas is used as process gas, and strong reducing gas, such as SiH.sub.4 (monosilane) gas acts on WF.sub.6 so as to generate vapor phase reaction. Then, a tungsten film is formed on the entire surface of the substrate, and a hole is filled with the tungsten film. After filling the hole with the tungsten film, an unnecessary tungsten film, which is formed on portions other than the hole, is removed by etch-back.
Among these three methods, the entire surface film formation etch-back method, which is mainly used, will be specially explained with reference to FIGS. 3A to 3E.
FIGS. 3A to 3E show the steps of filling the via hole, which is used to perform the electrical connection between the interconnections, by the entire surface film formation etch-back method. As shown in FIG. 3A, an insulating film 4, made of, e.g., SiO.sub.2, is formed on a substrate 2 of a semiconductor wafer. A first wiring layer 6, made of a patterned aluminum film, is formed on the insulating film 4. An antireflection film 8, made of, e.g., a TiN film, is formed on the first wiring layer 6 to carry out a good resist exposure. In the figure, 10 denotes an interlayer insulating film (interlevel insulator), which is made of, e.g., SiO.sub.2. The interlayer insulating film covers the entire surface of the upper portion of the substrate 2. In this case, electrical elements (not shown) are also entirely covered with the interlayer insulating film 10.
The via hole 12 is formed to reach the first wiring layer 6 at a predetermined position of the interlayer insulating film 10. If the via hole 12 is filled with the tungsten film and tungsten directly contacts aluminum (first wiring layer 6), contact resistance is increased and adhesion of tungsten and aluminum is deteriorated by an absorbing effect occurred therebetween. In order to avoid such disadvantages, as shown in FIG. 3B, for example, a barrier metal 14, made of a Ti film and/or a TiN film, is formed on the entire surface including an inner surface of the hole 12 before filling the via hole 12 with the tungsten film. Thereafter, as shown in FIG. 3C, for example, a tungsten film 16 is formed on the entire surface of the barrier metal 14 by CVD so as to fill the hole 12. Next, as shown in 3D, an unnecessary portion of the tungsten film 16 and the barrier metal 14 are removed by etch back. As a result, a second patterned wiring layer 18, made of aluminum, is formed on the exposed interlayer insulating film 10 (FIG. 3E). The second wiring layer 18 is electrically connected to the first wiring layer 6 through tungsten filled in the via hole 12.
In the sputtering method, since the sputtering process is performed at a high temperature of 400 to 450.degree. C., it is impossible to use a low constant organic material having low heat resistance as an interlayer insulating film for the next generation. Moreover, in the sputtering method, the TiN film or the Ti film must be used as an underlying film to increase adhesion between the films and to realize good hole filling. Due to this, the number of film forming steps is increased, and the contact resistance becomes higher than the structure in which the Al films are directly connected to each other.
On the other hand, in the selective tungsten film forming method, since tungsten having a specific resistance, which is higher than aluminum, is used, a signal delay occurs and the operation speed of the device is reduced. Due to this, the selective tungsten film forming method cannot sufficiently answer the needs of the device, such as a microprocessor, in which a high speed operation is desired. Moreover, in the selective tungsten film forming method, the upper and lower wiring layers containing aluminum are connected to each other by tungsten, which is a different kind of metal from these layers. Due to this, electromigration and corrosion occur, and reliability of the wirings is reduced. Moreover, if the selective tungsten formation is broken by impurity material adhered to the surface of the conductive material in forming the tungsten film, interwire leakage is induced. In other words, if the selective deposition of the tungsten film on the surface of the conductive material is insufficient, the electrical connection is lost.
Also, in the entire surface film formation etch back method, since the tungsten having a high specific resistance is used, the same problem as the selective tungsten forming method occurs, and the contact resistance generated at the boundary between the films is increased. Moreover, in the entire surface film formation etch back method, the barrier metal 14 must be formed to control the electromigration and to maintain the adhesion. As a result, the number of film forming steps is increased. Then, as compared with the structure in which the Al films are directly connected to each other, the specific resistance is increased. Moreover, the process for forming the tungsten film on the entire surface by CVD is performed at a high temperature of 450.degree. C. Due to this, it is impossible to use a low dielectric constant organic material having low heat resistance as an interlayer insulating film. Moreover, the underlaying film such as barrier metal 14, when being formed, causes tungsten coverage to be lowered due to an increase in an aspect ratio in defining the connection hole. In the worst case, it impossible to fill the connection hole properly.
As mentioned above, if the via hole is filled with the tungsten or the aluminum by sputtering, various problems occur. On the other hand, no problem occurs when the via hole is filled with aluminum by CVD. The reason can be explained as follows.
Aluminum is low in cost, and has low resistance and good conductivity, and the covering property due to CVD is superior to the covering property due to sputtering, so that the generation of voids can be limited.
Therefore, it is desirable that the hole is filled with aluminum by CVD. However, in this case, aluminum is deposited on the hole in a crystal form having a relative large grain size. Due to this, if hole is filled with the aluminum at a volume fraction (occupation rate) of 100% to surely perform the electrical connection between the upper and lower layers, the aluminum rises from the hole, and a convex portion of aluminum is formed on the upper side of the hole. Then, if the wiring processing of the upper layer is further performed as the convex portion is left as it is, the focal depth exceeds its allowable range due to the height of the convex portion in lithography processing. As a result, the lithography processing cannot be carried out with high accuracy.